In the following the invention is explained with reference to synchronous dynamical random access memory (SDRAM). However, the invention is applicable to any kind of dynamical random access memory, e.g. double data rate RAM (DDR-RAM), enhanced synchronous DRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus DRAM (RDRAM), etc. Furthermore, the invention is also applicable to single-port static random access memory (single-port SRAM).
Typical SDRAM modules comprise four independent banks. Each bank consists of rows, which consist of columns. To access a datum the corresponding row on the corresponding bank is opened by the command ‘activate’ for reading and writing. After activation, which needs 2 to 4 cycles, the data transfer is initiated by sending a ‘read’ or ‘write’ command together with the column address. After the transfer the bank is precharged, which again needs 2 to 4 cycles, to deactivate the open row and to prepare the bank for the next ‘activate’ command. The command ‘precharge’ closes the open row.
Typically a burst transfer is used for reading or writing several data with only one ‘read’ or ‘write’ command. The access starts at a selected location (column) and continues for a programmed number of locations. After initiating a new burst, the command bus is free and can be used to activate or precharge other banks.
In general, SDRAM is used for simultaneously storing CPU-instructions as well as data. The SDRAM is accessed through a cache. A linear access is achieved in the following way: first bank first row, second bank first row, third bank first row, fourth bank first row, first bank second row and so on. Assuming a linear access this allows to hide latency by activating the row on the next bank before the CPU/cache actually wants to access this row.
In an apparatus for reading from and/or writing to recording media, e.g. optical recording media such as digital versatile disks (DVD), a single SDRAM module is favorably used for storing instructions and data for an on-chip-CPU and for buffering the real-time data stream between a drive for the recording media and a host. In this case, to meet CPU latency constraints, the burst length of the buffer input and output stream need to be reduced to only a few beats. However, even using four beat bursts cannot nearly fulfill timing and throughput constraints, because the overhead caused by the four interfaces, i.e. CPU-instructions, CPU-data, input stream, and output stream, acts like random access. In particular, read and write access to the buffer is in random order. Therefore, since the next row is unknown, pre-activation of buffer banks is not possible.
To circumvent this problem and to eliminate latency caused by the ‘activate’ and ‘precharge’ commands, the SDRAM module can be replaced by static RAM (SRAM). Alternatively, the number of modules can be increased for reducing the workload of a single module, or the width of the data bus between the module and the application specific integrated circuit (ASIC) can be expanded for increasing the bandwidth. However, additional wiring is needed for these solutions, which is usually limited by the IC design. Therefore, this solution is in general not feasible. A further solution consists in de-coupling the buffer input and output, which can be performed by large on-chip SRAM buffering two or more complete rows. However, in this case a very complex logic is required for controlling the data flow.